The present invention relates to forming a flip chip semiconductor package with underfill, and more particularly to forming a flip chip semiconductor package with no-flow underfill.
Flip chip semiconductor packages formed with underfill material, which is also referred to simply as underfill, are known. Such a flip chip package comprises a semiconductor die which has a pattern of pads on one surface; a substrate with corresponding terminals on a pattern of conductors on a first surface, and a second surface, opposite the first surface, with a pattern of external conductors; solder interconnects that couple the die pads to the terminals; and underfill that fills the gap between the die and the substrate.
A relatively well known, method of forming a flip chip package is to first raise or bump the pads on the semiconductor die with solder, then flip the semiconductor die over and place it with the bumps on the terminals. When the assembly of the semiconductor die, substrate and solder bumps is reflowed, the solder between the pads and terminals melt to form solder interconnects between the pads and the corresponding terminals.
Subsequently, the underfill is applied at the edges of the gap between the flipped semiconductor die and the substrate. Typically, the underfill is an epoxy-based liquid with a viscosity that significantly decreases under elevated temperature. Through capillary action, and under the elevated temperature, the underfill is drawn in, flows into, and fills the gap between the semiconductor die and the substrate.
The process of filling the gap with underfill presents a variety of difficulties, most of which relate to incomplete filling of the gap with the underfill, especially when bump pitch and height become smaller. For example when the pitch is less than 150 xcexcm, and the height is less than 50 xcexcm.
A relatively new method of forming a flip chip package attempts to shorten the process flow and in particular overcome the problems of applying underfill using no-flow underfill. U.S. Pat. No. 6,180,696, assigned to Georgia Tech Research Corporation of the USA, discloses a composition of no-flow underfill, and U.S. Pat. No. 5,128,746 by Pennisi et al., assigned to Motorola Inc. of the USA discloses a method for using no-flow underfill to form a semiconductor package.
With this method, a composition of no-flow underfill is applied to a first surface of a substrate that has the terminals thereon, where the no-flow underfill covers or submerges the terminals. Then, the bumped semiconductor die is flipped and placed on the first surface of the substrate so that the bumps on the semiconductor die abut the terminals. The assembly is then reflowed so that the bumps will change to molten state and form interconnects between the pads and the terminals, with the underfill filling the gap between the die and the substrate. Hence, this method can substantially address the problems and difficulties associated with incomplete filling of the gap between the substrate and the semiconductor die with underfill.
Typically, no-flow underfill is an epoxy based organic compound and as is known by those skilled in the art, the coefficient of thermal expansion (CTE) of an organic compound is relatively high, in the range of 50xcx9c90 parts per million per degree Celsius (ppm/xc2x0 C.). Underfill with a high CTE is unable to efficiently ameliorate the mismatch between the CTE of the semiconductor die and the CTE of the substrate. Consequently, due to this mismatch in CTE, the solder joints between the pads of the semiconductor chip and the substrate in a semiconductor package are prone to thermo-mechanical failure. Thus, adversely affecting the reliability of such no-flow underfilled semiconductor package.
In flip chip semiconductor packages with smaller dies, say less than 5 millimeters (mm)xc3x975 mm, the CTE mismatch is tolerable, in that reliability tends to meet specified limits. However, with larger dies of 10 mmxc3x9710 mm and above, the CTE mismatch is more acute and the reliability is not within specified limits. Consequently, no-flow underfill is generally considered to be unsuitable for packaging such larger dies due to its poor CTE characteristics.
One known method of improving i.e. lowering the CTE of an underfill composition is by adding inorganic fillers such as silica to the underfill composition. However, no-flow underfill with filler results in open circuits between the pads on the semiconductor die and the terminals on the substrate.
The present invention seeks to provide a method for forming an underfilled semiconductor package, a semiconductor package formed thereby and a substrate therefor, which overcomes or at least reduces the abovementioned problems of the prior art.
Accordingly, in one aspect, the present invention provides a method for forming a flip chip semiconductor package, the method comprising the steps of:
a) providing a substrate having a first surface with plurality of raised terminal portions, wherein the plurality of raised terminal portions extend to at least the first surface, each of the raised terminal portions comprising a base portion and a free end portion, and at least the free end portions consisting of a first material having a first reflow temperature;
b) providing a semiconductor die having a plurality of pads on a first surface, wherein the plurality of pads have bumps thereon, each of the bumps comprising a base portion and a free end portion, at least the free end portions of the plurality of bumps consisting of the first material;
c) providing an underfill compound, wherein the underfill compound includes at least some inorganic filler to reduce the coefficient of thermal expansion (CTE) of the underfill compound;
d) disposing the underfill compound on the substrate;
e) placing the semiconductor die on the substrate with the underfill compound therebetween, wherein the free end portions of the plurality of bumps abut the free end portions of the plurality of raised terminal portions; and
f) reflowing the semiconductor die, the substrate and the underfill compound at substantially the first reflow temperature to form the at least the free end portions of the plurality of bumps and the at least the free end portions of the plurality of raised terminal portions into interconnects.
In another aspect the present invention provides a method for forming a flip chip semiconductor package, the method comprising the steps of:
a) providing a substrate having a first surface with a plurality of raised terminal portions, wherein the plurality of raised terminal portions extend to at least the first surface, each of the raised terminal portions comprising a base portion and a free end portion, at least the free end portions consisting of a first material having a first reflow temperature, wherein the first material is selected from the group consisting of tin-lead eutectic solder and lead-free solder;
b) providing a semiconductor die having a plurality of pads on a first surface, wherein the plurality of pads have bumps thereon, each of the bumps comprising a base portion and a free end portion, at least the free end portions of the plurality of bumps consisting of the first material;
c) providing an underfill compound, wherein the underfill compound includes at least some inorganic filler to reduce the coefficient of thermal expansion (CTE) of the underfill compound, wherein the inorganic filler is selected from the group consisting of silica, silicon nitride, boron nitride, and aluminum nitride;
d) disposing the underfill compound on the substrate;
e) placing the semiconductor die on the substrate with the underfill compound therebetween, wherein the free end portions of the plurality of bumps abut the free end portions of the plurality of raised terminal portions; and
f) reflowing the semiconductor die, the substrate and the underfill compound at substantially the first reflow temperature to form the at least the free end portions of the plurality of bumps and the at least the free end portions of the plurality of raised terminal portions into interconnects.
In yet another aspect the present invention provides a flip chip semiconductor package comprising:
a substrate having a plurality of raised terminal portions on a first surface and having a plurality of external interconnects;
a semiconductor die having a plurality of pads on a surface, the semiconductor die being flipped and disposed on the substrate with the first surface of the substrate opposite the surface of the semiconductor die, wherein the semiconductor die has a minimum area of 100 square millimeters;
a plurality of reflowed conductive interconnects extending between and electrically coupling the plurality of pads to the plurality of terminals; and
underfill compound filling between the first surface of the substrate and the surface of the semiconductor die, wherein the underfill compound includes at least some inorganic filler.
In still another aspect the present invention provides a substrate for a flip chip semiconductor package comprising:
an electrically non-conductive base layer;
a patterned layer of electrically conductive material disposed on the non-conductive base layer, the patterned layer of electrically conductive material having terminal locations;
a patterned layer of an electrically non-conductive material disposed on the patterned layer of electrically conductive material, the patterned layer of electrically non-conductive material having an exposed surface, and the patterned layer of electrically non-conductive material leaving at least some of the terminal locations uncovered; and
raised terminal portions on the terminal locations, wherein the raised terminal portions extend away from the terminal locations to at least the exposed surface of the patterned layer of the electrically nonconductive material.